The invention generally relates to an integrated circuit that has features to limit substrate current.
The operation of an integrated digital circuit may produce electrical activity that spans a wide frequency spectrum, including the radio frequency (RF) range. This high frequency electrical activity, such as the electrical activity in the RF range, has a tendency to generate a significant level of substrate current if no measures are taken to limit this current. To understand the origin of the substrate current, the digital circuit may be viewed as performing simple capacitive charge redistribution between loads that are being switched.
For example, FIG. 1 depicts an exemplary model 10 of a digital circuit, illustrating the current flows due to the switching of capacitive loads. More specifically, the model 10 includes switches 12 and 14 that couple respective capacitors 13 and 15 between a local supply voltage (called “VDD”) and a local ground 20. The capacitors 13 and 15 may represent the parasitic capacitances that are coupled to the switches. For example, if the switches 12 and 14 are implemented by metal oxide semiconductor field-effect-transistor (MOSFET) devices, then the capacitors 13 and 15 represent the load capacitances of these devices, such as parasitic device capacitances, capacitances of loads that are coupled to the devices, line capacitances, etc.
For purposes of controlling DC substrate currents, the switching devices of the integrated circuit typically are formed inside an n donor-type region (called a “deep n-well”) of a p donor-type substrate to provide a degree of isolation between the devices and the substrate. If high frequency electrical activity (electrical activity in the RF range or higher, for example) is present, however, a significant high frequency current path may develop between the deep n-well and the substrate. This current path, attributable to a parasitic capacitance that exists between the deep n-well and the substrate, is represented in FIG. 1 by a capacitor 24 that is coupled between the VDD local supply voltage and a substrate ground 26.
During a switching event, high frequency current flows in controlled current loops that are formed by the capacitors 13 and 15 and the switches 12 and 14. Also, current flows in less well-controlled loops that are formed by the capacitor 24. Thus, as depicted in FIG. 1, a substrate current flows through a current path 28 that exists between the substrate ground 26 and the local ground 20.
The substrate current typically presents challenges in that the current may cause interference with the operation of other unrelated circuits on the same semiconductor package that contains the digital circuit. Furthermore, the substrate current may introduce interference elsewhere in a system that incorporates the semiconductor package.
In an attempt to reduce the substrate current that is attributable to the high frequency electrical activity, a conventional digital circuit may include explicit bypass capacitors (collectively represented by a bypass capacitor 30 in FIG. 1) that are coupled between the VDD local supply voltage and the local ground 20. Neglecting resistive and inductive effects, the high frequency currents split between the loops containing the capacitor 24 and the loops containing the capacitor 30 according to the ratio of their respective capacitances. For example, if the capacitance of the capacitor 24 is approximately one tenth of the sum of the capacitance of the capacitors 24 and 30, then about ten percent of the high frequency current will flow through the poorly-controlled path 28 that includes the capacitor 24.
From this perspective, the risk of substrate current causing interference may be reduced by increasing the ratio of the capacitance of the capacitor 30 to the capacitance of the capacitor 24. However, challenges may arise in this type of compensation scheme in that by increasing the size of the bypass capacitor 30, the size of the deep n-well also increases. It follows that increasing the size of the deep n-well increases the area of contact between the deep n-well and the substrate, thereby also increasing the size of the capacitor 24. Therefore, there is a limit to this type of substrate current compensation.
Thus, there is a continuing need for better ways to limit a substrate current in an integrated circuit.